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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TMP112 sbos473f ? march 2009 ? revised february 2018 TMP112x high-accuracy, low-power, digital temperature sensors with smbus and two- wire serial interface in sot563 1 1 features 1 ? TMP112a accuracy without calibration : ? 0.5 c (maximum) from 0 c to +65 c (3.3 v) ? 1.0 c (maximum) from ? 40 c to +125 c ? TMP112b accuracy without calibration : ? 0.5 c (maximum) from 0 c to +65 c (1.8 v) ? 1.0 c (maximum) from ? 40 c to +125 c ? TMP112n accuracy without calibration: ? 1.0 c (maximum) from ? 40 c to +125 c ? sot563 package (1.6 mm 1.6 mm) ? low quiescent current: ? 10- a active (maximum), 1- a shutdown (maximum) ? supply range: 1.4 v to 3.6 v ? resolution: 12 bits ? digital output: smbus ? , two-wire, and i 2 c interface compatibility ? nist traceable 2 applications ? portable and battery-powered applications ? power-supply temperature monitoring ? computer peripheral thermal protection ? notebook computers ? battery management ? office machines ? thermostat controls ? electromechanical device temperatures ? general temperature measurements: ? industrial controls ? test equipment ? medical instrumentation 3 description the TMP112 family of devices are digital temperature sensors designed for high-accuracy, low-power, ntc/ptc thermistor replacements where high accuracy is required. the TMP112a and TMP112b offers 0.5 c accuracy and are optimized to provide the best psr performance for 3.3v and 1.8v operation respectively, while TMP112n offers 1 c accuracy. these temperature sensors are highly linear and do not require complex calculations or lookup tables to derive the temperature. the on-chip 12-bit adc offers resolutions down to 0.0625 c. the 1.6-mm 1.6-mm sot563 package is 68% smaller footprint than an sot23 package. the TMP112 family features smbus, two-wire and i 2 c interface compatibility, and allows up to four devices on one bus. the device also features an smbus alert function. the device is specified to operate over supply voltages from 1.4 to 3.6 v with the maximum quiescent current of 10 a over the full operating range. the TMP112 family is designed for extended temperature measurement in communication, computer, consumer, environmental, industrial, and instrumentation applications. the device is specified for operation over a temperature range of ? 40 c to +125 c. the TMP112 family production units are 100% tested against sensors that are nist-traceable and are verified with equipment that are nist-traceable through iso/iec 17025 accredited calibrations. device information (1) part number package body size (nom) TMP112x sot563 (6) 1.60 mm 1.20 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. block diagram productfolder diode temp. sensor ds a/d converter osc control logic serial interface config. and temp. register TMP112 temperature scl 13 64 alert sda gnd 2 5 v+add0 support &community tools & software technical documents ordernow referencedesign
2 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ..................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 timing requirements ................................................ 6 6.7 typical characteristics .............................................. 7 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 functional block diagrams ....................................... 9 7.3 feature description ................................................. 10 7.4 device functional modes ........................................ 17 7.5 programming .......................................................... 18 8 application and implementation ........................ 22 8.1 application information ............................................ 22 8.2 typical application ................................................. 22 9 power supply recommendations ...................... 23 10 layout ................................................................... 24 10.1 layout guidelines ................................................. 24 10.2 layout example .................................................... 24 11 device and documentation support ................. 25 11.1 documentation support ....................................... 25 11.2 community resources .......................................... 25 11.3 trademarks ........................................................... 25 11.4 electrostatic discharge caution ............................ 25 11.5 glossary ................................................................ 25 12 mechanical, packaging, and orderable information ........................................................... 25 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (december 2015) to revision f page ? added TMP112n and TMP112b orderables to the data sheet .............................................................................................. 1 ? removed duplicate specified and operating temperature ranges from the electrical characteristics table .......................... 5 ? removed calibrating for improved accuracy and using the slope specifications with a 1-point calibration sections ...... 22 changes from revision d (april 2015) to revision e page ? added ti design .................................................................................................................................................................... 1 ? added nist features bullet .................................................................................................................................................. 1 ? added last paragraph to description section ......................................................................................................................... 1 changes from revision c (october 2014) to revision d page ? changed min, typ, and max values for the temperature accuracy (temperature error) parameter .................................. 5 ? changed the frequency from 2.85 to 3.4 mhz in the power supply section of the electrical characteristics table ...... 5 ? changed the temperature error at 25 c graph in the typical characteristics section ......................................................... 7 ? changed the temperature error vs temperature graph in the typical characteristics section ............................................ 7 changes from revision b (june 2009) to revision c page ? added handling rating table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ............................................................... 4 ? changed parameters in timing requirements ...................................................................................................................... 6
3 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated changes from revision a (march 2009) to revision b page ? changed footnote 1 of specifications for user-calibrated systems table .......................................................................... 22 ? clarified example 1; extended worst-case accuracy to be from ? 15 c to +50 c ................................................................ 22 ? changed equation in using the slope specifications with a 1-point calibration ................................................................ 22 5 pin configuration and functions drl package 6-pin sot563 top view pin functions pin i/o description no. name 1 scl i serial clock. open-drain output; requires a pullup resistor. 2 gnd ? ground 3 alert o overtemperature alert. open-drain output; requires a pullup resistor. 4 add0 i address select. connect to gnd or v+ 5 v+ i supply voltage, 1.4 v to 3.6 v 6 sda i/o serial data. open-drain output; requires a pullup resistor. 12 3 65 4 sda v+ add0 scl gnd alert obs
4 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage v+ 5 v input voltage scl, add0, and sda ? 0.5 5 v input voltage alert ? 0.5 (v+) + 0.5 v output voltage ? 0.5 5 v operating temperature ? 55 150 c junction temperature, t j 150 c storage temperature, t stg ? 60 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101 (2) 1000 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v+ supply voltage 1.4 3.3 3.6 v t a operating free-air temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report. 6.4 thermal information thermal metric (1) TMP112 unit drl (sot563) 6 pins r ja junction-to-ambient thermal resistance 200 c/w r jc(top) junction-to-case (top) thermal resistance 73.7 c/w r jb junction-to-board thermal resistance 34.4 c/w jt junction-to-top characterization parameter 3.1 c/w jb junction-to-board characterization parameter 34.2 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w
5 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 6.5 electrical characteristics at t a = +25 c and v s = +1.4v to +3.6v, unless otherwise noted. parameter test conditions min typ max unit temperature input temperature range ? 40 +125 c accuracy (temperature error) TMP112a +25 c, v+ = 3.3 v 0.1 0.5 c 0 c to +65 c, v+ = 3.3 v 0.25 0.5 ? 40 c to +125 c 0.5 1 TMP112b +25 c, v+ = 1.8 v 0.1 0.5 0 c to +65 c, v+ = 1.8 v 0.25 0.5 ? 40 c to +125 c 0.5 1 TMP112n ? 40 c to +125 c 1 dc power-supply sensitivity ? 40 c to +125 c 0.0625 0.25 c/v long-term stability 3000 hours < 1 lsb resolution (lsb) 0.0625 c digital input/output input capacitance 3 pf v ih input logic level 0.7 (v+) 3.6 v v il ? 0.5 0.3 (v+) i in input current 0 < v in < 3.6 v 1 a v ol sda output logic level v+ > 2 v, i ol = 3 ma 0 0.4 v v+ < 2 v, i ol = 3 ma 0 0.2 (v+) v ol alert v+ > 2 v, i ol = 3 ma 0 0.4 v v+ < 2 v, i ol = 3 ma 0 0.2 (v+) resolution 12 bits conversion time 26 35 ms conversion modes cr1 = 0, cr0 = 0 0.25 conv/s cr1 = 0, cr0 = 1 1 cr1 = 1, cr0 = 0 (default) 4 cr1 = 1, cr0 = 1 8 timeout time 30 40 ms power supply operating supply range +1.4 +3.6 v i q average quiescent current serial bus inactive, cr1 = 1, cr0 = 0 (default) 7 10 a serial bus active, scl frequency = 400 khz 15 serial bus active, scl frequency = 3.4 mhz 85 i sd shutdown current serial bus inactive 0.5 1 a serial bus active, scl frequency = 400 khz 10 serial bus active, scl frequency = 3.4 mhz 80
6 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 6.6 timing requirements see the two-wire timing diagrams section for timing diagrams. fast mode high-speed mode unit min max min max ? (scl) scl operating frequency v+ 0.001 0.4 0.001 2.85 mhz t (buf) bus-free time between stop and start condition see figure 10 600 160 ns t (hdsta) hold time after repeated start condition. after this period, the first clock is generated. 600 160 ns t (susta) repeated start condition setup time 600 160 ns t (susto) stop condition setup time 600 160 ns t (hddat) data hold time 100 900 25 105 ns t (sudat) data setup time 100 25 ns t (low) scl-clock low period v+ , see figure 10 1300 210 ns t (high) scl-clock high period see figure 10 600 60 ns t fd data fall time see figure 10 300 80 ns t rd data rise time see figure 10 300 ns sclk 100 khz, see figure 10 1000 ns t fc clock fall time see figure 10 300 40 ns t rc clock rise time see figure 10 300 40 ns
7 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 6.7 typical characteristics at t a = +25 c and v+ = 3.3 v, unless otherwise noted. figure 1. temperature error at 25 c figure 2. accuracy vs supply figure 3. temperature error vs temperature four conversions per second figure 4. average quiescent current vs temperature figure 5. shutdown current vs temperature figure 6. quiescent current vs bus frequency (temperature at 3.3-v supply) temperature error ( q c) population -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 5 10 15 20 25 30 d001 - 0.250 - 0.225 - 0.200 - 0.175 - 0.150 - 0.125 - 0.100 - 0.075 - 0.050 - 0.025 0 0.0250.050 0.075 0.100 0.125 0.150 0.175 0.200 0.225 0.250 accuracy vs supply ( c/v) population temperature ( q c) temperature error ( q c) -60 -40 -20 0 20 40 60 80 100 120 140 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 d002 mean mean + 3 v mean 3 v 2018 16 14 12 10 86 4 2 0 temperature (c) -60 -20 40 60 140 160 i (a) q 3.6v supply -40 0 20 80 100 120 1.4v supply 100 9080 70 60 50 40 30 20 10 0 bus frequency (hz) 1k 10k 100k 1m 10m i (a) q -55c +25c +125c 10 98 7 6 5 4 3 2 1 0 temperature (c) -60 -40 0 40 140 160 i (a) sd 3.6v supply 1.4v supply -20 20 60 80 100 120
8 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated typical characteristics (continued) at t a = +25 c and v+ = 3.3 v, unless otherwise noted. figure 7. conversion time vs temperature 4038 36 34 32 30 28 26 24 22 20 temperature (c) -60 -20 40 60 140 160 conversion time (ms) 3.6v supply 1.4v supply -40 20 0 80 100 120
9 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the TMP112 family of devices are digital temperature sensors that are optimal for thermal-management and thermal-protection applications. the TMP112 family is two-wire, smbus, and i 2 c interface-compatible. the device is specified over an operating temperature range of ? 40 c to 125 c. figure 8 shows a block diagram of the TMP112 family. figure 9 shows the esd protection circuitry contained in the TMP112 family. the temperature sensor in the TMP112 family is the chip itself. thermal paths run through the package leads as well as the plastic package. the package leads provide the primary thermal path because of the lower thermal resistance of the metal. an alternative version of the TMP112 family is available. the tmp102 device has reduced accuracy, the same micro-package, and is pin-to-pin compatible. table 1. advantages of TMP112 family versus tmp102 device compatible interfaces package supply current supply voltage (min) supply voltage (max) resolution local sensor accuracy (max) specified calibration drift slope TMP112 family i 2 c smbus sot563 1.2 1.6 0.6 10 a 1.4 v 3.6 v 12 bit 0.0625 c 0.5 c: (0 c to 65 c) 1 c: (-40 c to 125 c) yes tmp102 i 2 c smbus sot563 1.2 1.6 0.6 10 a 1.4 v 3.6 v 12 bit 0.0625 c 2 c: (25 c to 85 c) 3 c: (-40 c to 125 c) no 7.2 functional block diagrams figure 8. internal block diagram diode temp. sensor ds a/d converter osc control logic serial interface config. and temp. register TMP112 temperature scl 13 64 alert sda gnd 2 5 v+add0
10 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated functional block diagrams (continued) (1) the resolution for the temperature adc in internal temperature mode is 0.0625 c/count. figure 9. equivalent internal esd circuitry 7.3 feature description 7.3.1 digital temperature output the digital output from each temperature measurement conversion is stored in the read-only temperature register. the temperature register of the TMP112 family is configured as a 12-bit read-only register (setting the em bit to 0 in the configuration register; see the extended mode (em) section), or as a 13-bit read-only register (setting the em bit to 1 in the configuration register) that stores the output of the most recent conversion. two bytes must be read to obtain data and are listed in table 8 and table 9 . byte 1 is the most significant byte (msb), followed by byte 2, the least significant byte (lsb). the first 12 bits (13 bits in extended mode) are used to indicate temperature. the least significant byte does not have to be read if that information is not needed. the data format for temperature is listed in table 2 and table 3 . one lsb equals 0.0625 c. negative numbers are represented in binary twos complement format. following power up or reset, the temperature register reads 0 c until the first conversion is complete. bit d0 of byte 2 indicates normal mode (em bit equals 0) or extended mode (em bit equals 1), and can be used to distinguish between the two temperature register data formats. the unused bits in the temperature register always read 0. table 2. 12-bit temperature data format (1) temperature ( c) digital output (binary) hex 128 0111 1111 1111 7ff 127.9375 0111 1111 1111 7ff 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4b0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 ? 0.25 1111 1111 1100 ffc ? 25 1110 0111 0000 e70 ? 55 1100 1001 0000 c90 alert core scl gnd v+ a0 v+ sda TMP112
11 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated table 2 does not list all temperatures. use the following rules to obtain the digital data format for a given temperature or the temperature for a given digital data format. to convert positive temperatures to a digital data format: 1. divide the temperature by the resolution 2. convert the result to binary code with a 12-bit, left-justified format, and msb = 0 to denote a positive sign. example: (50 c) / (0.0625 c / lsb) = 800 = 320h = 0011 0010 0000 to convert a positive digital data format to temperature: 1. convert the 12-bit, left-justified binary temperature result, with the msb = 0 to denote a positive sign, to a decimal number. 2. multiply the decimal number by the resolution to obtain the positive temperature. example: 0011 0010 0000 = 320h = 800 (0.0625 c / lsb) = 50 c to convert negative temperatures to a digital data format: 1. divide the absolute value of the temperature by the resolution, and convert the result to binary code with a 12-bit, left-justified format. 2. generate the twos complement of the result by complementing the binary number and adding one. denote a negative number with msb = 1. example: (| ? 25 c|) / (0.0625 c / lsb) = 400 = 190h = 0001 1001 0000 two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000 to convert a negative digital data format to temperature: 1. generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with msb = 1, denoting negative temperature result) by complementing the binary number and adding one. this represents the binary number of the absolute value of the temperature. 2. convert to decimal number and multiply by the resolution to get the absolute temperature, then multiply by ? 1 for the negative sign. example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1 convert to temperature: 0001 1001 0000 = 190h = 400; 400 (0.0625 c / lsb) = 25 c = (| ? 25 c|); (| ? 25 c|) ( ? 1) = ? 25 c table 3. 13-bit temperature data format temperature ( c) digital output (binary) hex 150 0 1001 0110 0000 0960 128 0 1000 0000 0000 0800 127.9375 0 0111 1111 1111 07ff 100 0 0110 0100 0000 0640 80 0 0101 0000 0000 0500 75 0 0100 1011 0000 04b0 50 0 0011 0010 0000 0320 25 0 0001 1001 0000 0190 0.25 0 0000 0000 0100 0004 0 0 0000 0000 0000 0000 ? 0.25 1 1111 1111 1100 1ffc ? 25 1 1110 0111 0000 1e70 ? 55 1 1100 1001 0000 1c90
12 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7.3.2 serial interface the TMP112 family operates as a slave device only on the smbus, two-wire, and i 2 c interface-compatible bus. connections to the bus are made through the open-drain i/o lines, sda and scl. the sda and scl pins feature integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. the TMP112 family supports the transmission protocol for both fast (1 khz to 400 khz) and high-speed (1 khz to 2.85 mhz) modes. all data bytes are transmitted msb first.. 7.3.2.1 bus overview the device that initiates the transfer is called a master , and the devices controlled by the master are slaves . the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. to address a specific device, a start condition is initiated, indicated by pulling the data-line (sda) from a high- to low-logic level when the scl pin is high. all slaves on the bus shift in the slave address byte on the rising edge of the clock, with the last bit indicating whether a read or write operation is intended. during the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge and pulling the sda pin low. a data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. during the data transfer the sda pin must remain stable when the scl pin is high, because any change in the sda pin when the scl pin is high is interpreted as a start or stop signal. when all data have been transferred, the master generates a stop condition indicated by pulling the sda pin from low to high when the scl pin is high. 7.3.2.2 serial bus address to communicate with the device, the master must first address slave devices through a slave-address byte. the slave-address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation. the TMP112 family features an address pin to allow up to four devices to be addressed on a single bus. table 4 describes the pin logic levels used to properly connect up to four devices. table 4. address pin and slave addresses device two-wire address a0 pin connection 1001000 ground 1001001 v+ 1001010 sda 1001011 scl 7.3.2.3 writing and reading operation accessing a particular register on the TMP112 family is accomplished by writing the appropriate value to the pointer register. the value for the pointer register is the first byte transferred after the slave address byte with the r/ w bit low. every write operation to the TMP112 family requires a value for the pointer register (see figure 11 ). when reading from the TMP112 family, the last value stored in the pointer register by a write operation is used to determine which register is read by a read operation. to change the register pointer for a read operation, a new value must be written to the pointer register. this action is accomplished by issuing a slave-address byte with the r/ w bit low, followed by the pointer register byte. no additional data are required. the master can then generate a start condition and send the slave address byte with the r/ w bit high to initiate the read command. see figure 12 for details of this sequence. if repeated reads from the same register are desired, continuously sending the pointer register bytes is not necessary because the TMP112 family retains the pointer register value until the value is changed by the next write operation. register bytes are sent with the most significant byte first, followed by the least significant byte.
13 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7.3.2.4 slave mode operations the TMP112 family can operate as a slave receiver or slave transmitter. as a slave device, the TMP112 family never drives the scl line. 7.3.2.4.1 slave receiver mode the first byte transmitted by the master is the slave address with the r/ w bit low. the TMP112 family then acknowledges reception of a valid address. the next byte transmitted by the master is the pointer register. the TMP112 family then acknowledges reception of the pointer register byte. the next byte or bytes are written to the register addressed by the pointer register. the TMP112 family acknowledges reception of each data byte. the master can terminate data transfer by generating a start or stop condition. 7.3.2.4.2 slave transmitter mode the first byte transmitted by the master is the slave address with the r/ w bit high. the slave acknowledges reception of a valid slave address. the next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. the master acknowledges reception of the data byte. the next byte transmitted by the slave is the least significant byte. the master acknowledges reception of the data byte. the master can terminate data transfer by generating a not-acknowledge on reception of any data byte or by generating a start or stop condition. 7.3.2.5 smbus alert function the TMP112 family supports the smbus alert function. when the TMP112 family operates in interrupt mode (tm = 1), the alert pin can be connected as an smbus alert signal. when a master senses that an alert condition is present on the alert line, the master sends an smbus alert command (0001 1001) to the bus. if the alert pin is active, the device acknowledges the smbus alert command and responds by returning the slave address on the sda line. the eighth bit (lsb) of the slave address byte indicates if the alert condition is caused by the temperature exceeding t (high) or falling below t (low) . the lsb is high if the temperature is greater than t (high) , or low if the temperature is less than t (low) . refer to the figure 13 section for details of this sequence. if multiple devices on the bus respond to the smbus alert command, arbitration during the slave address portion of the smbus alert command determines which device clears the alert status of that device. the device with the lowest two-wire address wins the arbitration. if the TMP112 family wins the arbitration, the TMP112 family alert pin becomes inactive at the completion of the smbus alert command. if the TMP112 family loses the arbitration, the TMP112 family alert pin remains active. 7.3.2.6 general call the TMP112 family responds to a two-wire general-call address (0000 000) if the eighth bit is 0. the device acknowledges the general-call address and responds to commands in the second byte. if the second byte is 0000 0110, the TMP112 family internal registers are reset to power-up values. the TMP112 family does not support the general-address acquire command. 7.3.2.7 high-speed (hs) mode for the two-wire bus to operate at frequencies above 400 khz, the master device must issue an hs-mode master code (0000 1xxx) as the first byte after a start condition to switch the bus to high-speed operation. the TMP112 family does not acknowledge this byte, but switches the input filters on the sda and scl pins and the output filters on the sda pin to operate in hs-mode, thus allowing transfers at up to 2.85 mhz. after the hs- mode master code has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. the bus continues to operate in hs-mode until a stop condition occurs on the bus. upon receiving the stop condition, the TMP112 family switches the input and output filters back to fast-mode operation. 7.3.2.8 timeout function the TMP112 family resets the serial interface if the scl pin is held low for 30 ms (typical) between a start and stop condition. the TMP112 family releases the sda line if the scl pin is pulled low and waits for a start condition from the host controller. to avoid activating the timeout function, maintain a communication speed of at least 1 khz for scl operating frequency.
14 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7.3.2.9 timing diagrams the TMP112 family is two-wire, smbus and i 2 c interface-compatible. figure 10 to figure 13 describe the various operations on the TMP112 family. parameters for figure 10 are defined in timing requirements . bus definitions are: bus idle: both sda and scl lines remain high. start data transfer: a change in the state of the sda line, from high to low, when the scl line is high, defines a start condition. each data transfer is initiated with a start condition. stop data transfer: a change in the state of the sda line from low to high when the scl line is high defines a stop condition. each data transfer is terminated with a repeated start or stop condition. data transfer: the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master device. the TMP112 family can also be used for single byte updates. to update only the ms byte, terminate the communication by issuing a start or stop communication on the bus. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. setup and hold times must be taken into account. on a master receive, the termination of the data transfer can be signaled by the master generating a not-acknowledge ('1') on the last byte that has been transmitted by the slave. 7.3.2.9.1 two-wire timing diagrams see the timing requirements . figure 10. two-wire timing diagram scl sda t (low) t rc t fc t (hdsta) t (hdsta) t (hddat) t (sudat) t (high) t (susta) t (susto) t (buf) s s p p t rd t fd
15 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated figure 11. two-wire timing diagram for write word format frame 1 two-wire slave address byte frame 2 pointer register byte frame 4 data byte 2 1 start by master ack by TMP112 ack by TMP112 ack by TMP112 stop by master 1 9 1 1 d7 d6 d5 d4 d3 d2 d1 d0 9 frame 3 data byte 1 ack by TMP112 1 d7 sda (continued) scl (continued) d6 d5 d4 d3 d2 d1 d0 9 9 sda scl 0 0 1 0 a1 (1) a0 (1) r/w 0 0 0 0 0 0 p1 p0 ? ? note: (1) the values of a0 and a1 are determined by the add0 pin.
16 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated figure 12. two-wire timing diagram for read word format figure 13. timing diagram for smbus alert frame 1 two-wire slave address byte frame 2 pointer register byte 1 start by master ack by TMP112 ack by TMP112 frame 3 two-wire slave address byte frame 4 data byte 1 read register start by master ack by TMP112 ack by master (2) from TMP112 1 9 1 9 1 9 1 9 sda scl 0 0 1 r/w 0 0 0 0 0 0 p1 p0 ? ? ? sda (continued) scl (continued) sda (continued) scl (continued) 1 0 0 1 0 a1 (1) a0 (1) 0 a1 (1) a0 (1) r/w d7 d6 d5 d4 d3 d2 d1 d0 frame 5 data byte 2 read register stop by master ack by master (3) from TMP112 1 9 d7 d6 d5 d4 d3 d2 d1 d0 stop by master note: (1) the values of a0 and a1 are determined by the add0 pin. (2) master should leave sda high to terminate a single-byte read operation.(3) master should leave sda high to terminate a two-byte read operation. note: (1) the values of a0 and a1 are determined by the add0 pin. frame 1 smbus alert response address byte frame 2 slave address from TMP112 start by master ack by TMP112 from TMP112 nack by master stop by master 1 9 1 9 sda scl alert 0 0 0 1 1 0 0 r/ w 1 0 0 1 a1 a0 status
17 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 continuos-conversion mode the default mode of the TMP112 family is continuos conversion mode. during continuous-conversion mode, the adc performs continuos temperature conversions and stores each results to the temperature register, overwriting the result from the previous conversion. the conversion rate bits, cr1 and cr0, configure the TMP112 family for conversion rates of 0.25 hz, 1 hz, 4 hz, or 8 hz. the default rate is 4 hz. the TMP112 family has a typical conversion time of 26 ms. to achieve different conversion rates, the TMP112 family makes a conversion and then powers down and waits for the appropriate delay set by cr1 and cr0. table 5 lists the settings for cr1 and cr0. table 5. conversion rate settings cr1 cr0 conversion rate 0 0 0.25 hz 0 1 1 hz 1 0 4 hz (default) 1 1 8 hz after a power-up or general-call reset, the TMP112 family immediately begins a conversion as shown in figure 14 . the first result is available after 26 ms (typical). the active quiescent current during conversion is 40 a (typical at +27 c). the quiescent current during delay is 2.2 a (typical at +27 c). (1) delay is set by cr1 and cr0. figure 14. conversion start 7.4.2 extended mode (em) the extended mode bit configures the device for normal mode operation (em = 0) or extended mode operation (em = 1). in normal mode, the temperature register and the high and low limit registers use a 12-bit data format. normal mode is used to make the TMP112 family compatible with the tmp75 device. extended mode (em = 1) allows measurement of temperatures above 128 c by configuring the temperature register and the high and low limit registers for 13-bit data format. 7.4.3 one-shot/conversion ready mode (os) the TMP112 family features a one-shot temperature-measurement mode. when the device is in shutdown mode, writing a 1 to the os bit begins a single temperature conversion. during the conversion, the os bit reads 0. the device returns to the shutdown state at the completion of the single conversion. after the conversion, the os bit reads 1. this feature is useful for reducing power consumption in the TMP112 family when continuous temperature monitoring is not required. as a result of the short conversion time, the TMP112 family can achieve a higher conversion rate. a single conversion typically occurs for 26 ms and a read can occur in less than 20 s. when using one-shot mode, 30 or more conversions per second are possible. 7.4.4 thermostat mode (tm) the thermostat mode bit indicates to the device whether to operate in comparator mode (tm = 0 ) or interrupt mode (tm = 1). startup start of conversion delay (1) 26ms 26ms
18 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7.4.4.1 comparator mode (tm = 0) in comparator mode (tm = 0), the alert pin is activated when the temperature equals or exceeds the value in the t (high) register and remains active until the temperature falls below the value in the t (low) register. for more information on the comparator mode, see the high- and low-limit register section. 7.4.4.2 interrupt mode (tm = 1) in interrupt mode (tm = 1), the alert pin is activated when the temperature exceeds t (high) or goes below t (low) registers. the alert pin is cleared when the host controller reads the temperature register. for more information on the interrupt mode, see the high- and low-limit register section. 7.5 programming 7.5.1 pointer register figure 15 shows the internal register structure of the TMP112 family. the 8-bit pointer register of the device is used to address a given data register. the pointer register uses the two lsbs (see table 13 ) to identify which of the data registers must respond to a read or write command. the power-up reset value of p1/p0 is '00'. by default, the TMP112 family reads the temperature on power-up. figure 15. internal register structure table 6 lists the pointer address of the registers available in the TMP112 family. table 7 lists the bits of the pointer register byte. during a write command, bytes p2 through p7 must always be 0. table 6. pointer addresses p1 p0 register 0 0 temperature register (read only) 0 1 configuration register (read/write) 1 0 t low register (read/write) 1 1 t high register (read/write) table 7. pointer register byte p7 p6 p5 p4 p3 p2 p1 p0 0 0 0 0 0 0 register bits i/o control interface sclsda temperature register configuration register t low register t high register pointer register
19 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 7.5.2 temperature register the temperature register of the TMP112 family is configured as a 12-bit read-only register (setting the em bit to 0 in the configuration register; see the extended mode section), or as a 13-bit read-only register (setting the em bit to 1 in the configuration register) that stores the output of the most recent conversion. two bytes must be read to obtain data and are listed in table 8 and table 9 . byte 1 is the most significant byte (msb), followed by byte 2, the least significant byte (lsb). the first 12 bits (13 bits in extended mode) are used to indicate temperature. the least significant byte does not have to be read if that information is not needed. table 8. byte 1 of temperature register byte d7 d6 d5 d4 d3 d2 d1 d0 1 t11 t10 t9 t8 t7 t6 t5 t4 (t12) (t11) (t10) (t9) (t8) (t7) (t6) (t5) (1) extended mode 13-bit configuration shown in parentheses. table 9. byte 2 of temperature register (1) byte d7 d6 d5 d4 d3 d2 d1 d0 2 t3 t2 t1 t0 0 0 0 0 (t4) (t3) (t2) (t1) (t0) (0) (0) (1) 7.5.3 configuration register the configuration register is a 16-bit read/write register used to store bits that control the operational modes of the temperature sensor. read/write operations are performed msb first. table 10 lists the format and power-up and reset values of the configuration register. for compatibility, the first byte corresponds to the configuration register in the tmp75 and tmp275 devices. all registers are updated byte by byte. table 10. configuration and power-up/reset formats byte d7 d6 d5 d4 d3 d2 d1 d0 1 os r1 r0 f1 f0 pol tm sd 0 1 1 0 0 0 0 0 2 cr1 cr0 al em 0 0 0 0 1 0 1 0 0 0 0 0 7.5.3.1 shutdown mode (sd) the shutdown mode bit saves maximum power by shutting down all device circuitry other than the serial interface, reducing current consumption to typically less than 0.5 a. shutdown mode is enabled when the sd bit = 1; the device shuts down when current conversion is completed. when sd = 0, the device maintains a continuous conversion state. 7.5.3.2 thermostat mode (tm) the thermostat mode bit indicates to the device whether to operate in comparator mode (tm = 0) or interrupt mode (tm = 1). for more information on comparator and interrupt modes, see the high- and low-limit registers section. 7.5.3.3 polarity (pol) the polarity bit allows the user to adjust the polarity of the alert pin output. if the pol bit is set to 0 (default), the alert pin becomes active low . when the pol bit is set to 1, the alert pin becomes active high and the state of the alert pin is inverted. the operation of the alert pin in various modes is illustrated in figure 16 .
20 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated figure 16. output transfer function diagrams 7.5.3.4 fault queue (f1/f0) a fault condition exists when the measured temperature exceeds the user-defined limits set in the t high and t low registers. additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. the fault queue is provided to prevent a false alert as a result of environmental noise. the fault queue requires consecutive fault measurements in order to trigger the alert function. table 11 lists the number of measured faults that may be programmed to trigger an alert condition in the device. for t high and t low register format and byte order, see the high- and low-limit registers section. table 11. TMP112 family fault settings f1 f0 consecutive faults 0 0 1 0 1 2 1 0 4 1 1 6 7.5.3.5 converter resolution (r1 and r0) the converter resolution bits, r1 and r0, are read-only bits. the TMP112 family converter resolution is set on start up to 11 which sets the temperature register to a 12-bit resolution. 7.5.3.6 one-shot (os) when the device is in shutdown mode, writing a 1 to the os bit begins a single temperature conversion. during the conversion, the os bit reads 0. the device returns to the shutdown state at the completion of the single conversion. for more information on the one-shot conversion mode, see the one-shot/conversion ready mode (os) section. 7.5.3.7 extended mode (em) the extended mode bit configures the device for normal mode operation (em = 0) or extended mode operation (em = 1). in normal mode, the temperature register and the high and low limit registers use a 12-bit data format. for more information on the extended mode, see the extended mode (em) section. measured temperature t high t low sn1511004 alert pin (comparator mode) pol = 0 sn1511004 alert pin (interrupt mode) pol = 0 sn1511004 alert pin (comparator mode) pol = 1 sn1511004 alert pin (interrupt mode) pol = 1 read read time read
21 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated (1) extended mode 13-bit configuration shown in parenthesis. 7.5.3.8 alert (al) the al bit is a read-only function. reading the al bit provides information about the comparator mode status. the state of the pol bit inverts the polarity of data returned from the al bit. when the pol bit equals 0, the al bit reads as 1 until the temperature equals or exceeds t (high) for the programmed number of consecutive faults, causing the al bit to read as 0. the al bit continues to read as 0 until the temperature falls below t (low) for the programmed number of consecutive faults, when it again reads as 1. the status of the tm bit does not affect the status of the al bit. 7.5.4 high- and low-limit register the temperature limits are stored in the t (low) and t (high) registers in the same format as the temperature result, and their values are compared to the temperature result on every conversion. the outcome of the comparison drives the behavior of the alert pin, which operates as a comparator output or an interrupt, and is set by the tm bit in the configuration register. in comparator mode (tm = 0), the alert pin becomes active when the temperature equals or exceeds the value in the t (high) register and generates a consecutive number of faults according to fault bits f1 and f0. the alert pin remains active until the temperature falls below the indicated t (low) value for the same number of faults. in interrupt mode (tm = 1), the alert pin becomes active when the temperature equals or exceeds the value in t (high) for a consecutive number of fault conditions (as shown in table 11 ). the alert pin remains active until a read operation of any register occurs, or the device successfully responds to the smbus alert response address. the alert pin is also cleared if the device is placed in shutdown mode. when the alert pin is cleared, it becomes active again only when temperature falls below t (low) , and remains active until cleared by a read operation of any register or a successful response to the smbus alert response address. when the alert pin is cleared, the above cycle repeats, with the alert pin becoming active when the temperature equals or exceeds t (high) . the alert pin can also be cleared by resetting the device with the general-call reset command. this action also clears the state of the internal registers in the device, returning the device to comparator mode (tm = 0). both operating modes are represented in figure 16 . table 12 and table 13 list the format for the t high and t low registers. the most significant byte is sent first, followed by the least significant byte. the power-up reset values for t (high) and t (low) are: ? t high = +80 c ? t low = +75 c the format of the data for t high and t low is the same as for the temperature register. table 12. bytes 1 and 2 of t high register (1) byte d7 d6 d5 d4 d3 d2 d1 d0 1 h11 h10 h9 h8 h7 h6 h5 h4 (h12) (h11) (h10) (h9) (h8) (h7) (h6) (h5) byte d7 d6 d5 d4 d3 d2 d1 d0 2 h3 h2 h1 h0 0 0 0 0 (h4) (h3) (h2) (h1) (h0) (0) (0) (0) (1) extended mode 13-bit configuration shown in parenthesis. table 13. bytes 1 and 2 of t low register (1) byte d7 d6 d5 d4 d3 d2 d1 d0 1 l11 l10 l9 l8 l7 l6 l5 l4 (l12) (l11) (l10) (l9) (l8) (l7) (l6) (l5) byte d7 d6 d5 d4 d3 d2 d1 d0 2 l3 l2 l1 l0 0 0 0 0 (l4) (l3) (l2) (l1) (l0) (0) (0) (0)
22 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TMP112 family is used to measure the pcb temperature of the board location where the device is mounted. the programmable address options allow up to four locations on the board to be monitored on a single serial bus. 8.2 typical application note: the scl, sda, and alert pins require pullup resistors. figure 17. typical connections 8.2.1 design requirements the TMP112 family requires pullup resistors on the scl, sda, and alert pins. the recommended value for the pullup resistors is 5 k . in some applications the pullup resistor can be lower or higher than 5 k but must not exceed 3 ma of current on any of those pins. a 0.01- f bypass capacitor on the supply is recommended as shown in figure 17 . the scl and sda lines can be pulled up to a supply that is equal to or higher than v+ through the pullup resistors. to configure one of four different addresses on the bus, connect the add0 pin to either the gnd, v+, sda, or scl pin. 8.2.2 detailed design procedure place the device in close proximity to the heat source that must be monitored, with a proper layout for good thermal coupling. this placement ensures that temperature changes are captured within the shortest possible time interval. to maintain accuracy in applications that require air or surface temperature measurement, take care to isolate the package and leads from ambient air temperature. a thermally-conductive adhesive is helpful in achieving accurate surface temperature measurement. scl gnd alert 2 4 1 add0 v+ 6 3 5 0.01 f two-wire host controller TMP112 1.4 v to 3.6 v sda pullup resistors supply bypass capacitor supply voltage 5 k
23 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated typical application (continued) the TMP112 family is a very low-power device and generates very low noise on the supply bus. applying an rc filter to the v+ pin of the TMP112 family can further reduce any noise that the device might propagate to other components. r (f) in figure 18 must be less than 5 k ? and c (f) must be greater than 10 nf. figure 18. noise reduction techniques 8.2.3 application curves figure 19 shows the step response of the TMP112 family to a submersion in an oil bath of 100 o c from room temperature (27 o c). the time-constant, or the time for the output to reach 63% of the input step, is 0.8 s. the time-constant result depends on the printed-circuit board (pcb) that the TMP112 family is mounted. for this test, the TMP112 family was soldered to a two-layer pcb that measured 0.375 inches 0.437 inches. figure 19. temperature step response 9 power supply recommendations the TMP112 family operates with power supply in the range of 1.4 to 3.6 v. the device is optimized for operation at 3.3-v supply but can measure temperature accurately in the full supply range. refer to the section for more information about the power supply impact on the accuracy of the device. a power-supply bypass capacitor is required for proper operation. place this capacitor as close as possible to the supply and ground pins of the device. a typical value for this supply bypass capacitor is 0.01 f. applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. time (s) temperature ( q c) -1 1 3 5 7 9 11 13 15 17 19 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 device scl sda gnd v+ alert add0 c (f) 10 nf r (f) 5 k supply voltage
24 TMP112 sbos473f ? march 2009 ? revised february 2018 www.ti.com product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines place the power-supply bypass capacitor as close as possible to the supply and ground pins. the recommended value of this bypass capacitor is 0.01 f. additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. pull up the open-drain output pins (sda , scl and alert) through 5- k pullup resistors. 10.2 layout example figure 20. layout example serial bus traces pull-up resistors supply bypass capacitor via to power or ground plane via to internal layer supply voltage scl gnd alert add0 v+ sda ground plane for thermal coupling to heat source heat source
25 TMP112 www.ti.com sbos473f ? march 2009 ? revised february 2018 product folder links: TMP112 submit documentation feedback copyright ? 2009 ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? tmp102 low-power digital temperature sensor with smbus and two-wire serial interface in sot563 (sbos397) ? tmpx75 temperature sensor with i 2 c and smbus interface in industry standard lm75 form factor and pinout (sbos288) ? tmp275 0.5 c temperature sensor with i 2 c and smbus interface in industry standard lm75 form factor and pinout (sbos363) ? ultralow power multi-sensor data logger with nfc interface design guide ? capacitive-based human proximity detection for system wake-up & interrupt design guide 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. smbus is a trademark of intel, inc. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 12-mar-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TMP112aidrlr active sot-5x3 drl 6 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 obs TMP112aidrlt active sot-5x3 drl 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 obs TMP112bidrlr preview sot-5x3 drl 6 4000 tbd call ti call ti -40 to 125 TMP112bidrlt preview sot-5x3 drl 6 250 tbd call ti call ti -40 to 125 TMP112naidrlr active sot-5x3 drl 6 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ab TMP112naidrlt active sot-5x3 drl 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1ab (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 12-mar-2018 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of TMP112 : ? automotive: TMP112-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TMP112aidrlr sot-5x3 drl 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 TMP112aidrlt sot-5x3 drl 6 250 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 TMP112naidrlr sot-5x3 drl 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 TMP112naidrlt sot-5x3 drl 6 250 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 package materials information www.ti.com 9-mar-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TMP112aidrlr sot-5x3 drl 6 4000 202.0 201.0 28.0 TMP112aidrlt sot-5x3 drl 6 250 202.0 201.0 28.0 TMP112naidrlr sot-5x3 drl 6 4000 183.0 183.0 20.0 TMP112naidrlt sot-5x3 drl 6 250 183.0 183.0 20.0 package materials information www.ti.com 9-mar-2018 pack materials-page 2

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own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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